Peter Moses here!
Pure mathematics is, in its way, the poetry of logical ideas.
- Albert Einstein
I'm a Computer Engineering Undergraduate student at the University of Texas at Arlington with a focus on High Performance Computing and AI/ML.
Activities and organizations I'm involved in:
- UTA's National Society of Black Engineers
- Association of Computer Machinery at UTA
Leadership I've been involved in:
- Freshman Leaders on Campus (FLOC) during my freshman year
- Being a student advocate for our school's CAHSI chapter whereby my goal was to bring awareness about the organization and its initiatives
My long term goal is to use technology and math to solve really hard and fascinating problems and through that, positively impact the world.
I'm always looking for opportunities to both learn and actively apply my current knowledge.
Standalone Projects
This is a high-performance, feature-rich command-line calculator in C++17 capable of evaluating complex, multi-term mathematical expressions. The core of the project is a sophisticated parsing engine built on classic compiler and systems programming principles. Mathematical expressions are evaluated using the Shunting Yard Algorithm.
For my other ongoing work, check out my current repositories on my GitHub.
Site Tools
An interactive Karnaugh Map solver supporting 2-6 variables with all standard logic gates (AND, OR, NOT, NAND, NOR, XOR, XNOR). Features include don't-care states, SOP/POS minimization, XOR/XNOR pattern detection, minterm/maxterm notation, and manual cell entry mode.
Interactive bit manipulation visualizer with step-by-step expression evaluation, variable bank with multiple format displays, and a quick reference for common bit tricks.
Compare binary adder architectures (Ripple Carry, Carry Lookahead, Carry Select, Carry Save) side-by-side with animated carry propagation and area-speed tradeoff analysis.
Multiplier Architecture Visualizer
Compare binary multiplier architectures (Shift-and-Add, Booth's Radix-2, Array, Wallace Tree) side-by-side with animated partial product reduction and area-speed tradeoff analysis.
Generate interactive gate-level circuit diagrams from boolean expressions with SVG export.
Interactive limit order book with step-by-step matching visualization. Place limit and market orders, walk through price-time priority matching, and explore scenarios like level sweeping, spread collapse, and iceberg orders.
Bite-sized explanations of computer engineering concepts, building blocks, and the theory behind the tools.
Publications
Publications and research papers will be listed here once available.
Resume
Contact
I'm always down for a coffee chat, questions, greetings. Reach me at:
pxm4277[at]mavs[dot]uta[dot]edu